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16-bit, 80/100 msps adc ad9446 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features 100 msps guaranteed sampling rate (ad9446-100) 83.6 dbfs snr with 30 mhz input (3.8 v p-p input, 80 msps) 82.6 dbfs snr with 30 mhz input (3.2 v p-p input, 80 msps) 89 dbc sfdr with 30 mhz input (3.2 v p-p input, 80 msps) 95 dbfs 2-tone sfdr with 9.8 mhz and 10.8 mhz (100 msps) 60 fsec rms jitter excellent linearity dnl = 0.4 lsb typical inl = 3.0 lsb typical 2.0 v p-p to 4.0 v p-p differential full-scale input buffered analog inputs lvds outputs (ansi-644 compatible) or cmos outputs data format select (offset binary or twos complement) output clock available 3.3 v and 5 v supply operation applications mri receivers multicarrier, multimode cellular receivers antenna array positioning power amplifier linearization broadband wireless radar infrared imaging communications instrumentation general description the ad9446 is a 16-bit, monolithic, sampling analog-to-digital converter (adc) with an on-chip track-and-hold circuit. it is optimized for performance, small size, and ease of use. the product operates up to a 100 msps, providing superior snr for instrumentation, medical imaging, and radar receivers employing baseband (<100 mhz) if frequencies. the adc requires 3.3 v and 5.0 v power supplies and a low voltage differential input clock for full performance operation. no external reference or driver components are required for many applications. data outputs are cmos or lvds compatible (ansi-644 compatible) and include the means to reduce the overall current needed for short trace distances. functional block diagram cmos or lvds output staging clock and timing management agnd drgnd drvdd vref clk+ vin+ ad9446 vin? clk? dco 05490-001 avdd1 avdd2 dcs mode dfs output mode t/h buffer 16 pipeline adc 2 32 2 or d15 to d0 ref refb sense reft figure 1. optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data mode. the ad9446 is available in a pb-free, 100-lead, surface-mount, plastic package (100-lead tqfp/ep) specified over the industrial temperature range ?40c to +85c. product highlights 1. true 16-bit linearity. 2. high performance: outstanding snr performance for baseband ifs in data acquisition, instrumentation, magnetic resonance imaging, and radar receivers. 3. ease of use: on-chip reference and high input impedance track-and-hold with adjustable analog input range and an output clock simplifies data capture. 4. packaged in a pb-free, 100-lead tqfp/ep package. 5. clock duty cycle stabilizer (dcs) maintains overall adc performance over a wide range of clock pulse widths. 6. or (out-of-range) outputs indicate when the signal is beyond the selected input range.
ad9446 rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specifications ......................................................................... 3 ac specifications .......................................................................... 4 digital specifications ................................................................... 6 switching specifications .............................................................. 6 timing diagrams .......................................................................... 7 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 ter mi nolo g y .......................................................................................9 pin configurations and function descriptions ......................... 10 equivalent circuits ......................................................................... 15 typical performance characteristics ........................................... 16 theory of operation ...................................................................... 24 analog input and reference overview ................................... 24 clock input considerations ...................................................... 26 power considerations ................................................................ 27 digital outputs ........................................................................... 27 timing ......................................................................................... 27 operational mode selection ..................................................... 28 evaluation board ............................................................................ 29 outline dimensions ....................................................................... 36 ordering guide .......................................................................... 36 revision history 10/05revision 0: initial version
ad9446 rev. 0 | page 3 of 36 specifications dc specifications avdd1 = 3.3 v, avdd2 = 5.0 v, drvdd = 3.3 v, lvds mode, specifie d minimum sampling rate, 3.2 v p-p differential input, internal trimmed reference (1.6 v mode), a in = ?1.0 dbfs, dcs on, unless otherwise noted. table 1. ad9446bsvz-80 ad9446bsvz-100 parameter temp min typ max min typ max unit resolution full 16 16 bits accuracy no missing codes full guaranteed guaranteed offset error full ?5 0.1 +5 ?5 0.1 +5 mv gain error full ?3 0.6 +3 ?3 0.5 +3 % fsr 25c ?2 0.3 +2 ?2 0.3 +2 % fsr differential nonlinearity (dnl) 1 full ?0.75 0.4 +0.75 ?0.85 0.4 +0.85 lsb integral nonlinearity (inl) 1 25c ?5 3.0 +5 ?6 3.0 +6 lsb voltage reference output voltage 1 vref = 1.6 v (3.2 v p-p analog input range) full 1.6 1.6 v load regulation @ 1.0 ma full 2 2 mv reference input current (external 1.6 v reference) full a input referred noise 25c 1.5 1.9 lsb rms analog input input span vref = 1.6 v full 3.2 3.2 v p-p vref = 1.0 v (external) full 2.0 2.0 v p-p internal input common-mode voltage full 3.5 3.5 v external input common-mode voltage full 3.2 3.8 3.2 3.8 v input resistance 2 full 1 1 k input capacitance 2 full 6 6 pf power supplies supply voltage avdd1 full 3.14 3.3 3.46 3.14 3.3 3.46 v avdd2 full 4.75 5.0 5.25 4.75 5.0 5.25 v drvddlvds outputs full 3.0 3.3 3.6 3.0 3.3 3.6 v drvddcmos outputs full 3.0 3.3 3.6 3.0 3.3 3.6 v supply current i avdd 1 full 335 365 368 401 ma i avdd2 1 full 204 234 223 255 ma i drvdd 1 lvds outputs full 68 75 69 75 ma i drvdd 1 cmos outputs full 14 14 ma psrr offset full 1 1 mv/v gain full 0.2 0.2 %/v power consumption lvds outputs full 2.4 2.6 2.6 2.8 w cmos outputs (dc input) full 2.2 2.3 w 1 measured at the maximum clock rate, f in = 15 mhz, full-scale sine wave, with a 100 differential termination on each pair of output bits for lvds output mode and approximately 5 pf loading on each output bit for cmos output mode. 2 input capacitance or resistance refers to the effective impedance between one differential input pin and agnd. refer to figure 6 for the equivalent analog input structure.
ad9446 rev. 0 | page 4 of 36 ac specifications avdd1 = 3.3 v, avdd2 = 5.0 v, drvdd = 3.3 v, lvds mode, specifie d minimum sample rate, 3.2 v p-p differential input, internal trimmed reference (1.6 v mode), a in = ?1 dbfs, dcs on, unless otherwise noted. table 2. ad9446bsvz-80 ad9446bsvz-100 parameter temp min typ max min typ max unit signal-to-noise ratio (snr) f in = 10 mhz 25c 79.6 81.8 78.4 79.7 db f in = 30 mhz 25c 80.5 81.6 78.3 79.5 db full 79.2 77.9 db f in = 70 mhz 25c 79.0 80.6 77.7 79.0 db full 78.2 77.6 db f in = 92 mhz 25c 80.1 78.9 db f in = 125 mhz 25c 78.8 78.2 db f in = 170 mhz 25c 77.1 77.0 db f in = 10 mhz (2 v p-p input) 25c 78.3 76.6 db f in = 30 mhz (2 v p-p input) 25c 78.3 76.6 db f in = 70 mhz (2 v p-p input) 25c 77.6 76.2 db f in = 92 mhz (2 v p-p input) 25c 77.5 76 db f in = 125 mhz (2 v p-p input) 25c 76.7 75.6 db f in = 170 mhz (2 v p-p input) 25c 75.5 75.1 db signal-to-noise and distortion (sinad) f in = 10 mhz 25c 77.1 80.5 76.9 78.9 db f in = 30 mhz 25c 75.9 80.4 75.5 78.6 db full 74.9 71.7 db f in = 70 mhz 25c 75.5 78.6 73.8 77.7 db full 74.4 69.1 db f in = 92 mhz 25c 79.2 77.1 db f in = 125 mhz 25c 74.9 76.9 db f in = 170 mhz 25c 66.0 70.5 db f in = 10 mhz (2 v p-p input) 25c 77.9 76.2 db f in = 30 mhz (2 v p-p input) 25c 77.8 76.1 db f in = 70 mhz (2 v p-p input) 25c 77.1 75.9 db f in = 92 mhz (2 v p-p input) 25c 77.1 75.7 db f in = 125 mhz (2 v p-p input) 25c 75.7 75.3 db f in = 170 mhz (2 v p-p input) 25c 72.5 73.6 db effective number of bits (enob) f in = 10 mhz 25c 13.2 13.0 bits f in = 30 mhz 25c 13.2 12.9 bits f in = 70 mhz 25c 12.9 12.8 bits f in = 92 mhz 25c 13.0 12.7 bits f in = 125 mhz 25c 12.3 12.6 bits f in = 170 mhz 25c 10.8 11.6 bits
ad9446 rev. 0 | page 5 of 36 ad9446bsvz-80 ad9446bsvz-100 parameter temp min typ max min typ max unit spurious-free dynamic range (sfdr, second or third harmonic) f in = 10 mhz 25c 82 90 82 92 dbc f in = 30 mhz 25c 82 89 82 89 dbc full 80 79 dbc f in = 70 mhz 25c 80 87 81 89 dbc full 79 77 dbc f in = 92 mhz 25c 84 84 dbc f in = 125 mhz 25c 80 83 dbc f in = 170 mhz 25c 66 74 dbc f in = 10 mhz (2 v p-p input) 25c 92 94 dbc f in = 30 mhz (2 v p-p input) 25c 93 92 dbc f in = 70 mhz (2 v p-p input) 25c 92 92 dbc f in = 92 mhz (2 v p-p input) 25c 90 89 dbc f in = 125 mhz (2 v p-p input) 25c 85 87 dbc f in = 170 mhz (2 v p-p input) 25c 77 82 dbc worst spur excluding second or third harmonics f in = 10 mhz 25c ?98 ?89 ?96 ?91 dbc f in = 30 mhz 25c ?97 ?89 ?97 ?89 dbc full ?89 ?87 dbc f in = 70 mhz 25c ?98 ?90 ?96 ?90 dbc full ?89 ?88 dbc f in = 92 mhz 25c ?98 ?95 dbc f in = 125 mhz 25c ?96 ?96 dbc f in = 170 mhz 25c ?95 ?92 dbc f in = 10 mhz (2 v p-p input) 25c ?97 ?93 dbc f in = 30 mhz (2 v p-p input) 25c ?97 ?96 dbc f in = 70 mhz (2 v p-p input) 25c ?94 ?94 dbc f in = 92 mhz (2 v p-p input) 25c ?97 ?99 dbc f in = 125 mhz (2 v p-p input) 25c ?97 ?95 dbc f in = 170 mhz (2 v p-p input) 25c ?93 ?95 dbc two-tone sfdr f in = 10.8 mhz @ ?7 dbfs, 9.8 mhz @ ?7 dbfs 25c 96 95 dbfs f in = 70.3 mhz @ ?7 dbfs, 69.3 mhz @ ?7 dbfs 25c 92 92 dbfs analog bandwidth full 325 540 mhz
ad9446 rev. 0 | page 6 of 36 digital specifications avdd1 = 3.3 v, avdd2 = 5.0 v, drvdd = 3.3 v, r lvds_bias = 3.74 k, unless otherwise noted. table 3. ad9446bsvz-80 ad9446bsvz-100 parameter temp min typ max min typ max unit cmos logic inputs (dfs, dcs mode, output mode) high level input voltage full 2.0 2.0 v low level input voltage full 0.8 0.8 v high level input current full 200 200 a low level input current full ?10 +10 ?10 +10 a input capacitance full 2 2 pf digital output bitscmos mode (d0 to d15, otr) 1 drvdd = 3.3 v high level output voltage full 3.25 3.25 v low level output voltage full 0.2 0.2 v digital output bitslvds mode (d0 to d15, otr) v od differential output voltage 2 full 247 545 247 545 mv v os output offset voltage full 1.125 1.375 1.125 1.375 v clock inputs (clk+, clk?) differential input voltage full 0.2 0.2 v common-mode voltage full 1.3 1.5 1.6 1.3 1.5 1.6 v input resistance full 1.1 1.4 1.7 1.1 1.4 1.7 k input capacitance full 2 2 pf 1 output voltage levels measured with 5 pf load on each output. 2 lvds r term = 100 . switching specifications avdd1 = 3.3 v, avdd2 = 5.0 v, drvdd = 3.3 v, unless otherwise noted. table 4. ad9446bsvz-80 ad9446bsvz-100 parameter temp min typ max min typ max unit clock input parameters maximum conversion rate full 80 100 msps minimum conversion rate full 1 1 msps clk period full 12.5 10 ns clk pulse width high 1 (t clkh ) full 5.0 4.0 ns clk pulse width low 1 (t clkl ) full 5.0 4.0 ns data output parameters output propagation delaycmos (t pd ) 2 (dx, dco+) full 3.35 3.35 ns output propagation delaylvds (t pd ) 3 (dx+), (t cpd ) 3 (dco+) full 2.1 3.6 4.8 2.3 3.6 4.8 ns pipeline delay (latency) full 13 13 cycles aperture delay (t a ) full ns aperture uncertainty (jitter, t j ) full 60 60 fsec rms 1 with duty cycle stabilizer (dcs) enabled. 2 output propagation delay is measured from clock 50% transition to data 50% transition with 5 pf load. 3 lvds r term = 100 . measured from the 50% point of the rising edge of clk+ to the 50% poi nt of the data transition.
ad9446 rev. 0 | page 7 of 36 timing diagrams n ? 13 n?12 n n + 1 a in clk+ clk? data out dco+ dco? n n + 1 n?1 t clkh t clkl 1/ f s t pd 13 clock cycles t cpd 05490-002 figure 2. lvds mode timing diagram n + 1 n + 2 n?1 t clkl 13 clock cycles 05490-003 n t clkh t pd vin clk+ clk? dx dco+ dco? n ? 13 n ? 12 n ? 1 n figure 3. cmos timing diagram
ad9446 rev. 0 | page 8 of 36 absolute maximum ratings table 5. parameter with respect to rating electrical avdd1 agnd ?0.3 v to +4 v avdd2 agnd ?0.3 v to +6 v drvdd dgnd ?0.3 v to +4 v agnd dgnd ?0.3 v to +0.3 v avdd1 drvdd ?4 v to +4 v avdd2 drvdd ?4 v to +6 v avdd2 avdd1 ?4 v to +6 v d0 to d15 dgnd C0.3 v to drvdd + 0.3 v clk+/clk? agnd C0.3 v to avdd1 + 0.3 v output mode, dcs mode, dfs agnd C0.3 v to avdd1 + 0.3 v vin+, vin? agnd C0.3 v to avdd2 + 0.3 v vref agnd C0.3 v to avdd1 + 0.3 v sense agnd C0.3 v to avdd1 + 0.3 v reft, refb agnd C0.3 v to avdd1 + 0.3 v environmental storage temperature range C65c to +125c operating temperature range C40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance the heat sink of the ad9446 package must be soldered to ground. table 6. package type ja jb jc unit 100-lead tqfp/ep 19.8 8.3 2 c/w typical ja = 19.8c/w (heat sink soldered) for multilayer board in still air. typical jb = 8.3c/w (heat sink soldered) for multilayer board in still air. typical jc = 2c/w (junction to exposed heat sink) represents the thermal resistance through heat sink path. airflow increases heat dissipation, effectively reducing ja . also, more metal directly in contact with the package leads from metal traces through holes, ground, and power planes reduces the ja . it is required that the exposed heat sink be soldered to the ground plane. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad9446 rev. 0 | page 9 of 36 terminology analog bandwidth (full power bandwidth) the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay (t a ) the delay between the 50% point of the rising edge of the clock and the instant at which the analog input is sampled. aperture uncertainty (jitter, t j ) the sample-to-sample variation in aperture delay. clock pulse width and duty cycle pulse width high is the minimum amount of time that the clock pulse should be left in the logic 1 state to achieve rated performance. pulse width low is the minimum time the clock pulse should be left in the low state. at a given clock rate, these specifications define an acceptable clock duty cycle. differential nonlinearity (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 16-bit resolution indicates that all 65,536 codes must be present over all operating ranges. effective number of bits (enob) the effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured sinad using the following formula: () 6.02 1.76 ? = sinad enob gain error the first code transition should occur at an analog value of ? lsb above negative full scale. the last transition should occur at an analog value of 1? lsb below the positive full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. integral nonlinearity (inl) the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. maximum conversion rate the clock rate at which parametric testing is performed. minimum conversion rate the clock rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. offset error the major carry transition should occur for an analog value of ? lsb below vin+ = vin?. offset error is defined as the deviation of the actual transition from that point. out-of-range recovery time the time it takes for the adc to reacquire the analog input after a transition from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. output propagation delay (t pd ) the delay between the clock rising edge and the time when all bits are within valid logic levels. power-supply rejection ratio the change in full scale from the value with the supply at the minimum limit to the value with the supply at the maximum limit. signal-to-noise and distortion (sinad) the ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. signal-to-noise ratio (snr) the ratio of the rms input signal amplitude to the rms value of the sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious component may be a harmonic. sfdr can be reported in dbc (that is, degrades as signal level is lowered) or dbfs (always related back to converter full scale). temp er atu re d r i f t the temperature drift for offset error and gain error specifies the maximum change from the initial (25c) value to the value at t min or t max . total harmonic distortion (thd) the ratio of the rms input signal amplitude to the rms value of the sum of the first six harmonic components. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product.
ad9446 rev. 0 | page 10 of 36 pin configurations and function descriptions 74 d10+ 73 d10? 72 d9+ 69 d8? 70 d8+ 71 d9? 75 drgnd 68 dco+ 67 dco? 66 d7+ 64 drvdd 63 drgnd 62 d6+ 61 d6? 60 d5+ 59 d5? 58 d4+ 57 d4? 56 d3+ 55 d3? 54 d2+ 53 d2? 52 d1+ 51 d1? 65 d7? pin 1 dnc = do not connect 100 agnd 99 agnd 98 agnd 97 avdd1 96 avdd1 95 avdd1 94 avdd1 93 avdd1 92 avdd1 91 agnd 90 or+ 89 or? 88 drvdd 87 drgnd 86 d15+ (msb) 85 d15? 84 d14+ 83 d14? 82 d13+ 81 d13? 80 d12+ 79 d12? 78 d11+ 77 d11? 76 drvdd 26 avdd2 27 avdd2 28 avdd2 29 avdd2 30 avdd2 31 avdd2 32 avdd1 33 avdd1 34 avdd1 35 avdd2 36 avdd1 37 avdd2 38 avdd1 39 agnd 40 clk+ 41 clk? 42 agnd 43 avdd1 44 avdd1 45 avdd1 46 agnd 47 drgnd 48 drvdd 49 d0? (lsb) 50 d0+ 2 dnc 3 output mode 4 dfs 7 sense 6 avdd1 5 lvds_bias 1 dcs mode 8 vref 9 agnd 10 reft 12 avdd2 13 avdd2 14 avdd2 15 avdd2 16 avdd2 17 avdd2 18 avdd1 19 avdd1 20 avdd1 21 agnd 22 vin+ 23 vin? 24 agnd 25 avdd2 11 refb ad9446 lvds mode top view (not to scale) 05490-004 figure 4. 100-lead tqfp/ep pin configuration in lvds mode
ad9446 rev. 0 | page 11 of 36 table 7. pin function descriptions 100-lead tqfp/ep in lvds mode pin no. mnemonic description 1 dcs mode clock duty cycle stabilizer (dcs) control pin. cmos compatible. dcs = low (agnd) to enable dcs (recommended); dcs = high (avdd1) to disable dcs. 2 dnc do not connect. these pins should float. 3 output mode cmos-compatible output logic mode control pin. output mode = 0 for cmos mode; output mode = 1 (avdd1) for lvds outputs. 4 dfs data format select pin. cmos control pin that determines the format of the output data. dfs = high (avdd1) for twos complement; dfs = low (ground) for offset binary format. 5 lvds_bias set pin for lvds output current. place 3.7 k resistor terminated to drgnd. 6, 18 to 20, 32 to 34, 36, 38, 43 to 45, 92 to 97 avdd1 3.3 v (5%) analog supply. 7 sense reference mode selection. connect to agnd for internal 1.6 v reference (3.2 v p-p analog input range); connect to avdd1 for external reference. 8 vref 1.6 v reference i/o. function dependent on sense and external programming resistors. decouple to ground with 0.1 f and 10 f capacitors. 9, 21, 24, 39, 42, 46, 91, 98, 99, 100, exposed heat sink agnd analog ground. the exposed heat sink on the bottom of the package must be connected to agnd. 10 reft differential reference output. decoupled to ground with 0.1 f capacitor and to refb (pin 11) with 0.1 f and 10 f capacitors. 11 refb differential reference output. decoupled to gr ound with a 0.1 f capacitor and to reft (pin 10) with 0.1 f and 10 f capacitors. 12 to 17, 25 to 31, 35, 37 avdd2 5.0 v analog supply (5%). 22 vin+ analog inputtrue. 23 vin? analog inputcomplement. 40 clk+ clock inputtrue. 41 clk? clock inputcomplement. 47, 63, 75, 87, drgnd digital output ground. 48, 64, 76, 88 drvdd 3.3 v digital output supply (3.0 v to 3.6 v). 49 d0? (lsb) d0 complement output bit (lvds levels). 50 d0+ d0 true output bit. 51 d1? d1 complement output bit. 52 d1+ d1 true output bit. 53 d2? d2 complement output bit. 54 d2+ d2 true output bit. 55 d3? d3 complement output bit. 56 d3+ d3 true output bit. 57 d4? d4 complement output bit. 58 d4+ d4 true output bit. 59 d5? d5 complement output bit. 60 d5+ d5 true output bit. 61 d6? d6 complement output bit. 62 d6+ d6 true output bit. 65 d7? d7 complement output bit. 66 d7+ d7 true output bit. 67 dco? data clock outputcomplement. 68 dco+ data clock outputtrue. 69 d8? d8 complement output bit. 70 d8+ d8 true output bit. 71 d9? d9 complement output bit. 72 d9+ d9 true output bit. 73 d10? d10 complement output bit. 74 d10+ d10 true output bit. 77 d11? d11 complement output bit. 78 d11+ d11 true output bit.
ad9446 rev. 0 | page 12 of 36 pin no. mnemonic description 79 d12? d12 complement output bit. 80 d12+ d12 true output bit. 81 d13? d13 complement output bit 82 d13+ d13 true output bit. 83 d14? d14 complement output bit 84 d14+ d14 true output bit. 85 d15? d15 complement output bit. 86 d15+ (msb) d15 true output bit. 89 or? out-of-range complement output bit. 90 or+ out-of-range true output bit.
ad9446 rev. 0 | page 13 of 36 74 d4+ 73 d3+ 72 d2+ 69 dnc 70 d0+ (lsb) 71 d1+ 75 drgnd 68 dco+ 67 dco? 66 dnc 64 drvdd 63 drgnd 62 dnc 61 dnc 60 dnc 59 dnc 58 dnc 57 dnc 56 dnc 55 dnc 54 dnc 53 dnc 52 dnc 51 dnc 65 dnc pin 1 dnc = do not connect 100 agnd 99 agnd 98 agnd 97 avdd1 96 avdd1 95 avdd1 94 avdd1 93 avdd1 92 avdd1 91 agnd 90 or+ 89 d15+ (msb) 88 drvdd 87 drgnd 86 d14+ 85 d13+ 84 d12+ 83 d11+ 82 d10+ 81 d9+ 80 d8+ 79 d7+ 78 d6+ 77 d5+ 76 drvdd 26 avdd2 27 avdd2 28 avdd2 29 avdd2 30 avdd2 31 avdd2 32 avdd1 33 avdd1 34 avdd1 35 avdd2 36 avdd1 37 avdd2 38 avdd1 39 agnd 40 clk+ 41 clk? 42 agnd 43 avdd1 44 avdd1 45 avdd1 46 agnd 47 drgnd 48 drvdd 49 dnc 50 dnc 2 dnc 3 output mode 4 dfs 7 sense 6 avdd1 5 lvds_bias 1 dcs mode 8 vref 9 agnd 10 reft 12 avdd2 13 avdd2 14 avdd2 15 avdd2 16 avdd2 17 avdd2 18 avdd1 19 avdd1 20 avdd1 21 agnd 22 vin+ 23 vin? 24 agnd 25 avdd2 11 refb ad9446 cmos mode top view (not to scale) 05490-005 figure 5. 100-lead tqfp/ep pi n configuration in cmos mode
ad9446 rev. 0 | page 14 of 36 table 8. pin function descriptions100-lead tqfp/ep in cmos mode pin no. mnemonic description 1 dcs mode clock duty cycle stabilizer (dcs) control pin. cmos compatible. dcs = low (agnd) to enable dcs (recommended); dcs = high (avdd1) to disable dcs. 2, 49 to 62, 65 to 66, 69, dnc do not connect. these pins should float. 3 output mode cmos-compatible output logic mode control pin. output mode = 0 for cmos mode; output mode = 1 (avdd1) for lvds outputs. 4 dfs data format select pin. cmos control pin th at determines the format of the output data. dfs = high (avdd1) for twos complement; dfs = low (ground) for offset binary format. 5 lvds_bias set pin for lvds output current. place 3.7 k resistor terminated to drgnd. 6, 18 to 20, 32 to 34, 36, 38, 43 to 45, 92 to 97 avdd1 3.3 v (5%) analog supply. 7 sense reference mode selection. connect to agnd for internal 1 v reference; connect to avdd1 for external reference. 8 vref 1.6 v reference i/o. function dependent on sense and external programming resistors. decouple to ground with 0.1 f and 10 f capacitors. 9, 21, 24, 39, 42, 46, 91, 98, 99, 100, exposed heat sink agnd analog ground. the exposed heat sink on the bottom of the package must be connected to agnd. 10 reft differential reference output. decoupled to ground with 0.1 f capacitor and to refb (pin 11) with 0.1 f and 10 f capacitors. 11 refb differential reference output. decoupled to ground with a 0.1 f capacitor and to reft (pin 10) with 0.1 f and 10 f capacitors. 12 to 17, 25 to 31, 35, 37 avdd2 5.0 v analog supply (5%). 22 vin+ analog inputtrue. 23 vin? analog inputcomplement. 40 clk+ clock inputtrue. 41 clk? clock inputcomplement. 47, 63, 75, 87, drgnd digital output ground. 48, 64, 76, 88 drvdd 3.3 v digital output supply (3.0 v to 3.6 v). 67 dco? data clock outputcomplement. 68 dco+ data clock outputtrue. 70 d0+ (lsb) d0 true output bit (cmos levels). 71 d1+ d1 true output bit. 72 d2+ d2 true output bit. 73 d3+ d3 true output bit. 74 d4+ d4 true output bit. 77 d5+ d5 true output bit. 78 d6+ d6 true output bit. 79 d7+ d7 true output bit. 80 d8+ d8 true output bit. 81 d9+ d9 true output bit. 82 d10+ d10 true output bit. 83 d11+ d11 true output bit. 84 d12+ d12 true output bit. 85 d13+ d13 true output bit. 86 d14+ d14 true output bit. 89 d15+ (msb) d15 true output bit. 90 or+ out-of-range true output bit.
ad9446 rev. 0 | page 15 of 36 equivalent circuits x1 3.5v 1k 1k avdd2 vin+ vin? t/h avdd2 05490-006 6pf 6pf figure 6. equivalent analog input circuit 05490-007 1.2v drvdd drvdd k 3.74k i lvdsout lvdsbias figure 7. equivalent lvds_bias circuit drvdd dx? dx+ v v v v 05490-008 figure 8. equivalent lvds digital output circuit dx drvdd 05490-009 figure 9. equivalent cmos digital output circuit dcs mode, output mode, dfs vdd 30k 05490-010 figure 10. equivalent digital input circuit, dfs, dcs mode, output mode clk+ 3k 2.5k 3k 2.5k avdd2 clk? 05490-011 figure 11. equivalent sample clock input circuit
ad9446 rev. 0 | page 16 of 36 typical performance characteristics avdd1 = 3.3 v, avdd2 = 5.0 v, drvdd = 3.3 v, rated sample rate, lvds mode, dcs enabled, t a = 25c, 3.2 v p-p differential input, ain = ?1dbfs, internal trimmed reference (nominal vref = 1.6 v), unless otherwise noted. 0 ?130 0 50.0 05490-012 frequency (mhz) amplitude (dbfs) 100msps 10.3mhz @ ?1.0dbfs snr = 79.7db enob = 13.1bits sfdr = 90dbc ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 12.5 25.0 37.5 figure 12. ad9446-100 64k point single-tone fft/100 msps/10.3 mhz 0 ?130 0 50.0 05490-013 frequency (mhz) amplitude (dbfs) 100msps 30.3mhz @ ?1.0dbfs snr = 79.5db enob = 12.9bits sfdr = 90dbc ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 12.5 25.0 37.5 figure 13. ad9446-100 64k point single-tone fft/100 msps/30.3 mhz 0 ?130 0 50.0 05490-014 frequency (mhz) amplitude (dbfs) 100msps 70.3mhz @ ?1.0dbfs snr = 79.0db enob = 12.9bits sfdr = 86dbc ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 12.5 25.0 37.5 figure 14. ad9446-100 64k point single-tone fft/100 msps/70.3 mhz 0 ?130 0 50.0 05490-015 frequency (mhz) amplitude (dbfs) 100msps 92.16mhz @ ?1.0dbfs snr = 78.9db enob = 12.7bits sfdr = 84dbc ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 12.5 25.0 37.5 figure 15. ad9446-100 64k point single-tone fft/100 msps/92.16 mhz 0.6 ?0.6 0 05490-016 output code dnl error (msb) 0 65536 8192 16384 24576 32768 40960 49152 57344 0.4 0.2 0 ?0.2 ?0.4 figure 16. ad9446-100 dnl error vs . output code, 100 msps, 10.3 mhz 4 ?4 0 05490-017 output code inl error (msb) 0 65536 8192 16384 24576 32768 40960 49152 57344 3 2 1 0 ?1 ?2 ?3 figure 17. ad9446-100 inl error vs . output code, 100 msps, 10.3 mhz
ad9446 rev. 0 | page 17 of 36 0 ?130 0 05490-018 frequency (mhz) amplitude (dbfs) 80msps 10.3mhz @ ?1.0dbfs snr = 81.8db enob = 13.2bits sfdr = 90dbc ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 12.5 25.0 37.5 figure 18. ad9446-80 64k point single-tone fft/80 msps/10.3 mhz 0 ?130 0 05490-019 frequency (mhz) amplitude (dbfs) 80msps 30.3mhz @ ?1.0dbfs snr = 81.6db enob = 13.2bits sfdr = 89dbc ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 12.5 25.0 37.5 figure 19. ad9446-80 64k point single-tone fft/80 msps/30.3 mhz 0 ?130 0 05490-020 frequency (mhz) amplitude (dbfs) 80msps 70.3mhz @ ?1.0dbfs snr = 80.6db enob = 12.9bits sfdr = 85dbc ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 12.5 25.0 37.5 figure 20. ad9446-80 64k point single-tone fft/80 msps/70.3 mhz 0 ?130 0 05490-021 frequency (mhz) amplitude (dbfs) 80msps 100.3mhz @ ?1.0dbfs snr = 79.5db enob = 12.7bits sfdr = 92dbc ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 12.5 25.0 37.5 figure 21. ad9446-80 64k point single-tone fft/80 msps/100.3 mhz 0.6 ?0.6 0 05490-022 output code dnl error (msb) 0 65536 8192 16384 24576 32768 40960 49152 57344 0.4 0.2 0 ?0.2 ?0.4 figure 22. ad9446-80 dnl error vs. output code, 80 msps, 10.3 mhz 4 ?4 0 05490-023 output code inl error (msb) 0 65536 8192 16384 24576 32768 40960 49152 57344 3 2 1 0 ?1 ?2 ?3 figure 23. ad9446-80 inl error vs. output code, 80 msps, 10.3 mhz
ad9446 rev. 0 | page 18 of 36 95 70 0 180 05490-024 analog input frequency (mhz) (db) 20 40 60 80 100 120 140 160 90 85 80 75 sfdr (dbc) +85c sfdr (dbc) ?40c snr (db) +25c snr (db) +85c snr (db) ?40c sfdr (dbc) +25c figure 24. ad9446-100 snr/sfdr vs. analog input frequency, 100 msps, 3.2 v p-p 95 70 0 180 05490-025 analog input frequency (mhz) (db) 20 40 60 80 100 120 140 160 90 85 80 75 sfdr (dbc) +85c sfdr (dbc) ?40c snr (db) +25c snr (db) +85c snr (db) ?40c sfdr (dbc) +25c figure 25. ad9446-100 snr/sfdr vs. analog input frequency, 100 msps, 3.2 v p-p, cmos output mode 120 0 ?100 0 05490-026 analog input amplitude (db) (db) 100 80 60 40 20 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 snr db snr dbfs sfdr dbc sfdr dbfs figure 26. ad9446-100 snr/sfdr vs. analog input level, 100 msps 95 70 0 180 05490-027 analog input frequency (mhz) (db) 20 40 60 80 100 120 140 160 90 85 80 75 sfdr (dbc) +85c sfdr (dbc) ?40c snr (db) +25c snr (db) +85c snr (db) ?40c sfdr (dbc) +25c figure 27. ad9446-100 snr/sfdr vs. analog input frequency, 100 msps, 2.0 v p-p 86 77 78 1.8 4.2 05490-039 analog input range (v p-p) (db) 85 84 83 81 82 80 79 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 80m snr dbfs 100m snr dbfs figure 28. ad9446-100 snr vs. input range, 30.3 mhz, ?30 dbfs 130 0 ?100 0 05490-029 analog input amplitude (db) (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 snr db snr dbfs sfdr dbc sfdr dbfs 110 90 70 50 30 10 figure 29. ad9446-100 snr/sfdr vs. analog input level, 100 msps, cmos output mode
ad9446 rev. 0 | page 19 of 36 95 60 0 180 05490-030 analog input frequency (mhz) (db) 20 40 60 80 100 120 140 160 90 85 80 75 70 65 sfdr (dbc) +85c sfdr (dbc) ?40c snr (db) +25c snr (db) +85c snr (db) ?40c sfdr (dbc) +25c figure 30. ad9446-80 snr/sfdr vs. analog input frequency, 80 msps, 3.2 v p-p 95 60 0 180 05490-031 analog input frequency (mhz) (db) 20 40 60 80 100 120 140 160 90 85 80 75 70 65 sfdr (dbc) +85c sfdr (dbc) ?40c snr (db) +25c snr (db) +85c snr (db) ?40c sfdr (dbc) +25c figure 31. ad9446-80 snr/sfdr vs. analog input frequency, 80 msps, 3.2 v p-p, cmos mode 120 0 ?100 0 05490-032 analog input amplitude (db) (db) 100 80 60 40 20 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 snr db snr dbfs sfdr dbc sfdr dbfs figure 32. ad9446-80 snr/sfdr vs. analog input level, 80 msps 95 60 0 180 05490-033 analog input frequency (mhz) (db) 20 40 60 80 100 120 140 160 90 85 80 75 70 65 sfdr (dbc) +85c sfdr (dbc) ?40c snr (db) +25c snr (db) +85c snr (db) ?40c sfdr (dbc) +25c figure 33. ad9446-80 snr/sfdr vs. analog input frequency, 80 msps, 2.0 v p-p 90 70 72 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 05490-034 analog input common-mode voltage (db) snr db sfdr dbc 88 86 82 84 80 78 76 74 figure 34. ad9446-80 snr/sfdr vs. analog input common mode, 80 msps 120 0 ?100 0 05490-035 analog input amplitude (db) (db) 100 80 60 40 20 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 snr db snr dbfs sfdr dbc sfdr dbfs figure 35. ad9446-80 snr/sfdr vs. analog input level, 80 msps, cmos output mode
ad9446 rev. 0 | page 20 of 36 0 ?140 0 50.0 05490-037 frequency (mhz) amplitude (dbfs) 100msps 9.8mhz @ ?7.0dbfs 10.8mhz @ ?7.0dbfs sfdr = 95dbc 12.5 25.0 37.5 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 figure 36. ad9446-100 64k point two-tone fft/100 msps/9.8 mhz, 10.8 mhz 0 ?130 ?100 0 05490-038 fundamental level (db) spur and imd3 (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 sfdr dbfs sfdr dbc worst imd3 dbc worst imd3 dbfs ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 figure 37. ad9446-100 two-tone sfdr vs. analog input level 100 msps/ 9.8 mhz, 10.8 mhz 0 ?140 0 50.0 05490-040 frequency (mhz) amplitude (dbfs) 100msps 69.3mhz @ ?7.0dbfs 70.3mhz @ ?7.0dbfs sfdr = 92dbc 12.5 25.0 37.5 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 figure 38. ad9446-100 64k point two-tone fft/100 msps/69.3 mhz, 70.3 mhz 0 ?130 ?100 0 05490-041 fundamental level (db) spur and imd3 (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 sfdr dbfs sfdr dbc worst imd3 dbc worst imd3 dbfs ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 figure 39. ad9446-100 two-tone sfdr vs. analog input level 100 msps/ 69.3 mhz, 70.3 mhz 0 ?140 04 05490-042 frequency (mhz) amplitude (dbfs) 0 80msps 9.8mhz @ ?7.0dbfs 10.8mhz @ ?7.0dbfs sfdr = 96dbc 10 20 30 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 figure 40. ad9446-80 64k point two-tone fft/80 msps/9.8 mhz, 10.8 mhz 0 ?130 ?100 0 05490-043 fundamental level (db) spur and imd3 (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 sfdr dbfs sfdr dbc worst imd3 dbc worst imd3 dbfs ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 figure 41. ad9446-80 two-tone sfdr vs. analog input level 80 msps/ 9.8 mhz, 10.8 mhz
ad9446 rev. 0 | page 21 of 36 16000 0 05490-044 output code frequency n + 7 n + 6 n + 5 n + 4 n + 3 n + 2 n + 1 n n? 1 n? 2 n? 3 n? 4 n? 5 n? 6 n? 7 11 40 315 426 22 80 sample size = 65538 14000 12000 10000 8000 6000 4000 2000 1192 3424 7277 8376 4073 1458 11927 12619 14296 figure 42. ad9446-100 grounded input histogram 0 ?140 04 0 05490-045 frequency (mhz) amplitude (dbfs) 80msps 69.3mhz @ ?7.0dbfs 70.3mhz @ ?7.0dbfs sfdr = 92dbc 10 20 30 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 figure 43. ad9446-80 64k point two-tone fft/80 msps/69.3 mhz, 70.3 mhz 0 ?130 ?100 0 05490-046 fundamental level (db) spur and imd3 (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 sfdr dbfs sfdr dbc worst imd3 dbc worst imd3 dbfs ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 figure 44. ad9446-80 two-tone sfdr vs. analog input level 80 msps/ 69.3 mhz, 70.3 mhz 18000 0 05490-047 output code frequency n + 6 n + 5 n + 4 n + 3 n + 2 n + 1 n n? 1 n? 2 n? 3 n? 4 n? 5 n? 6 310 146 947 30 198 sample size = 65538 16000 14000 12000 10000 8000 6000 4000 2000 3916 4393 10145 11027 17090 16450 1181 figure 45. ad9446-80 grounded input histogram 0 ?0.8 ?40 05490-048 temperature (c) gain error (%fsr) ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 ?0.7 ?20 0 20 40 60 80 figure 46. ad9446-100 gain vs. temperature 400 0 0 05490-049 sample rate (msps) i supply (ma) 140 350 300 250 200 150 100 50 20 40 60 80 100 120 drvdd avdd2 avdd1 figure 47. ad9446-80 power supply current vs. sample rate 10.3 mhz @ ?1 dbfs
ad9446 rev. 0 | page 22 of 36 95 79 1.8 05490-050 analog input range (v p-p) (db) 4.2 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 10.3mhz sfdr dbc 30.3mhz sfdr dbc 93 91 89 87 85 83 81 70.3mhz sfdr dbc figure 48. ad9446-100/sfdr vs. analog input range, 100 msps 1.625 1.620 1.615 1.610 1.605 ?40 05490-051 temperature (c) vref ?20 0 20 40 60 80 figure 49. ad9446-100 vref vs. temperature 450 400 0 0 05490-063 sample rate (msps) i supply (ma) 140 350 300 250 200 150 100 50 20 40 60 80 100 120 drvdd avdd2 avdd1 figure 50. ad9446-100 power supply current vs. sample rate 10.3 mhz @ ?1 dbfs 82 76 1.8 05490-064 analog input range (v p-p) (db) 4.2 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 10.3mhz sfdr dbc 30.3mhz sfdr dbc 81 80 79 78 77 70.3mhz sfdr dbc figure 51. ad9446-100 snr vs. analog input range, 100 msps 95 79 1.8 05490-065 analog input range (v p-p) (db) 4.2 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 10.3mhz sfdr dbc 30.3mhz sfdr dbc 93 91 89 87 85 83 81 70.3mhz sfdr dbc figure 52. ad9446-80 sfdr vs. analog input range, 100 msps 84 77 1.8 05490-066 analog input range (v p-p) (db) 4.2 10.3mhz snr db 30.3mhz snr db 70.3mhz snr db 83 82 81 80 79 78 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 figure 53. ad9446-80/snr vs. analog input range, 80 msps
ad9446 rev. 0 | page 23 of 36 100 75 0 05490-036 sample rate (msps) (db) 95 90 85 80 2010 30 40 50 60 70 80 90 100 110 80m sfdr dbc 100m sfdr dbc 100m snr db 80m snr db figure 54. ad9446 single-tone snr/sfdr vs. sample rate 2.3 mhz
ad9446 rev. 0 | page 24 of 36 theory of operation the ad9446 architecture is optimized for high speed and ease of use. the analog inputs drive an integrated, high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 16-bit pipeline adc core. the device includes an on-board reference and input logic that accepts ttl, cmos, or lvpecl levels. the digital output logic levels are user selectable as standard 3 v cmos or lvds (ansi-644 compatible) via the output mode pin. analog input and reference overview a stable and accurate 0.5 v band gap voltage reference is built into the ad9446. the input range can be adjusted by varying the reference voltage applied to the ad9446, using either the internal reference or an externally applied reference voltage. the input span of the adc tracks reference voltage changes linearly. internal reference connection a comparator within the ad9446 detects the potential at the sense pin and configures the reference into three possible states, which are summarized in tabl e 9 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 55 ), setting vref to ~1.6 v. if a resistor divider is connected as shown in figure 56 , the switch again sets to the sense pin. this puts the reference amplifier in a noninverting mode with the vref output defined as ? ? ? ? ? ? += 15.0 in all reference configurations, reft and refb drive the analog-to-digital conversion core and establish its input span. the input range of the adc always equals twice the voltage at the reference pin for either an internal or an external reference. internal reference trim the internal reference voltage is trimmed during the production test; therefore, there is little advantage to the user supplying an external voltage reference to the ad9446. the gain trim is per- formed with the ad9446 input range set to 3.2 v p-p nominal (sense connected to agnd). because of this trim and the maximum ac performance provided by the 3.2 v p-p analog input range, there is little benefit to using analog input ranges <2 v p-p. however, reducing the range can improve sfdr performance in some applications. likewise, increasing the range up to 3.8 v p-p can improve snr. users are cautioned that the differential nonlinearity of the adc varies with the reference voltage. configurations that use <2.0 v p-p may exhibit missing codes and therefore degraded noise and distortion performance. 10 f + 0.1 f vref sense 0.5v ad9446 vin? vin+ reft 0.1 f 0.1 f 10 f 0.1 f refb select logic adc core + 05490-052 figure 55. internal reference configuration 05490-053 10 f + 0.1 f vref sense r2 r1 0.5v ad9446 vin? vin+ reft 0.1 f 0.1 f 10 f 0.1 f refb select logic adc core + figure 56. programmable reference configuration
ad9446 rev. 0 | page 25 of 36 table 9. reference configuration summary selected mode sense voltage resulting vref (v) resulting differential span (v p-p) external reference avdd n/a 2 external reference programmable reference 0.2 v to vref ? ? ? ? ? ? + r1 r2 1 (see figure 56 ) 2 vref programmable reference (set for 2 v p-p) 0.2 v to vref ? ? ? ? ? ? + r1 r2 1 , r1 = r2 = 1 k 2.0 programmable reference (set for 2 v p-p) 0.2 v to vref ? ? ? ? ? ? + r1 r2 1 , r1 = 1 k , r2 = 2.8 k 3.8 internal fixed reference agnd to 0.2 v 1.6 3.2 external reference operation when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equivalent 7 k load. the internal buffer still generates the positive and negative full-scale references, reft and refb, for the adc core. the input span is always twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 2.0 v. see figure 46 for gain variation vs. temperature. analog inputs as with most new high speed, high dynamic range adcs, the analog input to the ad9446 is differential. differential inputs improve on-chip performance because signals are processed through attenuation and gain stages. most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. there are also benefits at the pcb level. first, differential inputs have high common-mode rejection of stray signals, such as ground and power noise. second, they provide good rejection of common-mode signals, such as local oscillator feedthrough. the specified noise and distortion of the ad9446 cannot be realized with a single-ended analog input, so such configurations are discouraged. contact sales for recommendations of other 16-bit adcs that support single- ended analog input configurations. with the 1.6 v reference, which is the nominal value (see the internal reference trim section), the differential input range of the ad9446 analog input is nominally 3.2 v p-p or 1.6 v p-p on each input (vin+ or vin?). 3.5v vin+ vin? 1.6v p-p digital out = all 1s digital out = all 0s 05490-054 figure 57. differential analog input range for vref = 1.6 v the ad9446 analog input voltage range is offset from ground by 3.5 v. each analog input connects through a 1 k resistor to the 3.5 v bias voltage and to the input of a differential buffer. the internal bias network on the input properly biases the buffer for maximum linearity and range (see the equivalent circuits section). therefore, the analog source driving the ad9446 should be ac-coupled to the input pins. the recommended method for driving the analog input of the ad9446 is to use an rf transformer to convert single-ended signals to differential (see figure 58 ). series resistors between the output of the transformer and the ad9446 analog inputs help isolate the analog input source from switching transients caused by the internal sample-and-hold circuit. the series resistors, along with the 1 k resisters connected to the internal 3.5 v bias, must be considered in impedance matching the transformer input. for example, if r t is set to 51 , r s is set to 33 and there is a 1:1 impedance ratio transformer, the input will match a 50 source with a full-scale drive of 16.0 dbm. the 50 impedance matching can also be incorporated on the secondary side of the transformer, as shown in the evaluation board schematic (see figure 61 ).
ad9446 rev. 0 | page 26 of 36 05490-055 0.1 f r t ad9446 vin+ vin? r s r s adt1?1wt analog input signal figure 58. transformer-coupled analog input circuit clock input considerations any high speed adc is extremely sensitive to the quality of the sampling clock provided by the user. a track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-to- digital output. for that reason, considerable care was taken in the design of the clock inputs of the ad9446, and the user is advised to give careful thought to the clock source. typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to the clock duty cycle. commonly a 5% tolerance is required on the clock duty cycle to maintain dynamic performance charac- teristics. the ad9446 contains a clock duty cycle stabilizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nominal ~50% duty cycle. noise and distortion per- formance are nearly flat for a 30% to 70% duty cycle with the dcs enabled. the dcs circuit locks to the rising edge of clk+ and optimizes timing internally. this allows for a wide range of input duty cycles at the input without degrading performance. jitter in the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates of less than 30 mhz nominally. the loop is associated with a time constant that should be considered in applications where the clock rate can change dynamically, requiring a wait time of 1.5 s to 5 s after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. during the time that the loop is not locked, the dcs loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. in such an application, it may be appropriate to disable the duty cycle stabilizer. in all other applications, enabling the dcs circuit is recommended to maximize ac performance. the dcs circuit is controlled by the dcs mode pin; a cmos logic low (agnd) on dcs mode enables the duty cycle stabilizer, and logic high (avdd1 = 3.3 v) disables the controller. the ad9446 input sample clock signal must be a high quality, extremely low phase noise source to prevent degradation of per- formance. maintaining 16-bit accuracy places a premium on the encode clock phase noise. snr performance can easily degrade by 3 db to 4 db with 70 mhz analog input signals when using a high jitter clock source. (see the an-501 application note , aperture uncertainty and adc system performance.) for optimum performance, the ad9446 must be clocked differentially. the sample clock inputs are internally biased to ~1.5 v, and the input signal is usually ac-coupled into the clk+ and clk? pins via a transformer or capacitors. figure 59 shows one preferred method for clocking the ad9446. the clock source (low jitter) is converted from single-ended to differential using an rf trans- former. the back-to-back schottky diodes across the secondary of the transformer limit clock excursions into the ad9446 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9446 and limits the noise presented to the sample clock inputs. if a low jitter clock is available, it may help to band-pass filter the clock reference before driving the adc clock inputs. another option is to ac couple a differenti al ecl/pecl signal to the encode input pins, as shown in figure 60 . 05490-056 0.1 f ad9446 clk+ clk? hsms2812 diodes crystal sine source adt1?1wt figure 59. crystal clock oscillator, differential encode 05490-057 0.1 f ad9446 encode encode 0.1 f vt vt ecl/ pecl figure 60. differential ecl for encode itter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency ( f input ) and rms amplitude due only to aperture jitter ( t j ) can be calculated using the following equation: snr = 20 log[2 t j ] in the equation, the rms aperture jitter represents the root-mean- square of all jitter sources, which includes the clock input, analog input signal, and adc aperture jitter specification. if under- sampling applications are particularly sensitive to jitter the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9446. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or another method), it should be synchronized by the original clock during the last step.
ad9446 rev. 0 | page 27 of 36 power considerations care should be taken when selecting a power source. the use of linear dc supplies is highly recommended. switching supplies tend to have radiated components that may be received by the ad9446. each of the power supply pins should be decoupled as closely to the package as possible using 0.1 f chip capacitors. the ad9446 has separate digital and analog power supply pins. the analog supplies are denoted avdd1 (3.3 v) and avdd2 (5 v), and the digital supply pins are denoted drvdd. although the avdd1 and drvdd supplies can be tied together, best per- formance is achieved when the supplies are separate. this is because the fast digital output swings can couple switching current back into the analog supplies. note that both avdd1 and avdd2 must be held within 5% of the specified voltage. the drvdd supply of the ad9446 is a dedicated supply for the digital outputs in either lvds or cmos output mode. when in lvds mode, the drvdd should be set to 3.3 v. in cmos mode, the drvdd supply can be connected from 2.5 v to 3.6 v for compatibility with the receiving logic. digital outputs lvds mode the off-chip drivers on the chip can be configured to provide lvds-compatible output levels via pin 3 (output mode). lvds outputs are available when output mode is cmos logic high (or avdd1 for convenience) and a 3.74 k r set resistor is placed at pin 5 (lvds_bias) to ground. dynamic performance, including both sfdr and snr, is maximized when the ad9446 is used in lvds mode; designers are encouraged to take advantage of this mode. the ad9446 outputs include complimentary lvds outputs for each data bit (dx+/dx?), the overrange output (or+/or?), and the output data clock output (dco+/dco?). the r set resistor current is multiplied on-chip, setting the output current at each output equal to a nominal 3.5 ma (11 i r set ). a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing at the receiver. lvds mode facilitates interfacing with lvds receivers in custom asics and fpgas that have lvds capability for superior switching performance in noisy environments. single point-to-point net topologies are recommended, with a 100 termination resistor located as close to the receiver as possible. it is recommended to keep the trace length less than 2 inches and to keep differential output trace lengths as equal as possible. cmos mode in applications that can tolerate a slight degradation in dynamic performance, the ad9446 output drivers can be configured to interface with 2.5 v or 3.3 v logic families by matching drvdd to the digital supply of the interfaced logic. cmos outputs are available when output mode is cmos logic low (or agnd for convenience). in this mode, the output data bits, dx, are single-ended cmos, as is the overrange output, or+. the output clock is provided as a differential cmos signal, dco+/dco?. lower supply voltages are recommended to avoid coupling switching transients back to the sensitive analog sections of the adc. the capacitive load to the cmos outputs should be minimized, and each output should be connected to a single gate through a series resistor (220 ) to minimize switching transients caused by the capacitive loading. timing the ad9446 provides latched data outputs with a pipeline delay of 13 clock cycles. data outputs are available one propagation delay (t pd ) after the rising edge of clk+. refer to figure 2 and figure 3 for detailed timing diagrams.
ad9446 rev. 0 | page 28 of 36 operational mode selection data format select the data format select (dfs) pin of the ad9446 determines the coding format of the output data. this pin is 3.3 v cmos compatible, with logic high (or avdd1, 3.3 v) selecting twos complement and dfs logic low (agnd) selecting offset binary format. tabl e 1 0 summarizes the output coding. output mode select the ouput mode pin controls the logic compatibility, as well as the pinout of the digital outputs. this pin is a cmos- compatible input. with output mode = 0 (agnd), the ad9446 outputs are cmos compatible, and the pin assignment for the device is as defined in tabl e 8 . with output mode = 1 (avdd1, 3.3 v), the ad9446 outputs are lvds compatible, and the pin assignment for the device is as defined in tabl e 7 . duty cycle stabilizer the dcs circuit is controlled by the dcs mode pin; a cmos logic low (agnd) on dcs mode enables the dcs, and logic high (avdd1, 3.3 v) disables the controller. table 10. digital output coding code vin+ ? vin? input span = 3.2 v p-p (v) vin+ ? vin? input span = 2 v p-p (v) digital output offset binary (d15??????d0) digital output twos complement (d15??????d0) 65,536 +1.600 +1.000 1111 1111 1111 1111 0111 1111 1111 1111 32,768 0 0 1000 0000 0000 0000 0000 0000 0000 0000 32,767 ?0.0000488 ?0.000122 0111 1111 1111 1111 1111 1111 1111 1111 0 ?1.60 ?1.00 0000 0000 0000 0000 1000 0000 0000 0000
ad9446 rev. 0 | page 29 of 36 evaluation board evaluation boards are offered to configure the ad9446 in either cmos or lvds mode only. this design represents a recom- mended configuration for using the device over a wide range of sampling rates and analog input frequencies. these evaluation boards provide all the support circuitry required to operate the adc in its various modes and configurations. complete schematics are shown in figure 61 through figure 64 . gerber files are available from engineering applications demonstrating the proper routing and grounding techniques that should be applied at the system level. it is critical that signal sources with very low phase noise (<60 fsec rms jitter) be used to realize the ultimate performance of the converter. proper filtering of the input signal to remove harmonics and lower the integrated noise at the input is also necessary to achieve the specified noise performance. the evaluation boards are shipped with a 115 v ac to 6 v dc power supply. the evaluation boards include low dropout regulators to generate the various dc supplies required by the ad9446 and its support circuitry. separate power supplies are provided to isolate the dut from the support circuitry. each input configuration can be selected by proper connection of various jumpers (see figure 61 ). the lvds mode evaluation boards include an lvds-to-cmos translator, making them compatible with the high speed adc fifo evaluation kit (hsc-adc-e vala-sc). the kit includes a high speed data capture board that provides a hardware solution for capturing up to 32 kb samples of high speed adc output data in a fifo memory chip (user upgradeable to 256 kb samples). software is provided to enable the user to download the captured data to a pc via the usb port. this software also includes a behavioral model of the ad9446 and many other high speed adcs. behavioral modeling of the ad9446 is also available at www.analog.com/adisimadc . the adisimadc? software supports virtual adc evaluation using adi proprietary behavioral modeling technology. this allows rapid comparison between the ad9446 and other high speed adcs with or without hardware evaluation boards. the user can choose to remove the translator and terminations to access the lvds outputs directly.
ad9446 rev. 0 | page 30 of 36 optional 15 20 23 97 96 86 12 21 22 16 95 24 25 26 27 34 92 93 94 28 29 30 31 40 39 19 41 42 35 38 90 91 87 18 9 64 63 43 44 72 73 76 77 78 79 80 81 45 46 49 50 51 52 55 56 57 58 59 60 65 66 68 69 70 71 6 88 84 85 48 53 61 67 74 82 47 54 62 75 83 32 33 100 89 36 37 101 98 7 14 13 10 99 11 17 2 3 4 5 8 1 r11 1k vcc gnd r3 3.74k drgnd drvdd e24 extref d0_c (lsb) d0_t d1_c d1_t d3_c d3_t d4_c d4_t d5_c d5_t d7_c d7_t dr d8_c/d0_y d8_t/d1_y d9_c/d2_y d9_t/d3_y d10_c/d4_y c98 dnp gnd d15_c/d14_y e41 e25 e27 e26 vcc gnd e6 e5 e4 gnd c3 0.1 f c9 0.1 f c86 0.1 f r1 dnp gnd 5v vcc d14_c/d12_y drgnd d6_t d2_t drgnd d13_t/d11_y d10_t/d5_y drb d6_c d2_c drvdd d14_t/d13_y gnd vcc d13_c/d10_y d12_t/d9_y d12_c/d8_y d11_t/d7_y d11_c/d6_y drvdd vcc vcc gnd vcc vcc vcc 5v vcc encb gnd enc gnd vcc 5v vcc 5v gnd vcc 5v 5v 5v 5v 5v gnd sclk vcc vcc gnd vcc gnd 5v c13 dnp r35 33 r28 33 r9 dnp c91 0.1 f c8 0.1 f gnd gnd vcc gnd vcc epad ad9445/ad9446 u1 r4 36 p1 p2 p3 p22 ptmicro4 vcc 5v gnd gnd p4 1 2 3 4 p1 p2 p3 p21 ptmicro4 extref drvdd xtalpwr drgnd p4 1 2 3 4 dcs mode dnc output mode dfs lvdsbias avdd1 sense vref agnd reft refb avdd2 avdd2 avdd2 avdd2 avdd2 avdd2 avdd1 avdd1 avdd1 agnd vin+ vin? agnd avdd2 vcc drgnd dor_c dor_t/dor_y gnd vcc vcc drvdd (msb) d15_t/d15_y e1 e9 e10 gnd vcc e14 e2 e3 gnd vcc e66 e18 e19 gnd vcc c12 0.1 f c5 0.1 f j4 smbmst r5 dnp gnd tinb gnd analog l1 10nh e15 r6 36 r2 dnp c51 10 f c2 0.1 f c40 0.1 f gnd gnd 05490-059 drgnd d10_t d10_c d9_t d9_c d8_t d8_c dco dcob d7_t d7_c drvdd drgnd d6_t d6_c d5_t d5_c d4_t d4_c d3_t d3_c d2_t d2_c d1_t d1_c d12_t d12_c d11_t d11_c drvdd agnd agnd agnd avdd1 avdd1 avdd1 avdd1 or_c or_t agnd avdd1 avdd1 drvdd drgnd d15_t d15_c d14_t d14_c d13_t d13_c avdd2 avdd2 avdd2 avdd2 avdd2 avdd2 avdd1 avdd1 avdd1 avdd2 avdd1 avdd2 avdd1 enc agnd encb agnd avdd1 avdd1 avdd1 agnd drgnd drvdd d0_c d0_t h4 mthole6 gnd drgnd h3 mthole6 h1 mthole6 h2 mthole6 gnd c39 10 f + tout ct toutb c7 0.1 f pri sec gnd gnd t5 adt1-1wt t2 1 5 3 6 2 4 nc gnd gnd tinb toutb tout ct pri sec etc1-1-13 3 4 1 2 5 pri sec t1 etc1-1-13 15 34 2 figure 61. ad9446 evaluation board schematic
ad9446 rev. 0 | page 31 of 36 in out out1 5v c34 10 f c89 10 f 3 4 2 1 adp3338 u14 gnd gnd gnd 5vx 5vx 5vx 5v gnd vin gnd + + in out out1 3.3v l3 ferrite c6 10 f c87 10 f 3 4 2 1 adp3338 u7 gnd gnd vccx vccx gnd vin gnd + + in out out1 3.3v c4 10 f c88 10 f 3 4 2 1 adp3338 u3 drgnd drgnd drvdd x drvddx drgnd vin gnd + + pj-102a c33 10 f 1 3 2 p4 gnd vin + 1 3 2 power options adt1-1wt pri sec nc enc encb gnd j5 smbmst r7 dnp dnp r39 0 r8 50 c26 0.1 f c36 dnp 1 2 3 5 6 t3 2 3 1 cr2 cr1 c42 0.1 f gnd xtalinput gnd cr2 to make layout and parasitic loading symmetrical 4 j1 smbmst 1 3 2 encode gnd out vcc vee ~out + gnd gnd xtalinput e30 c1 10 f e31 8 14 7 u6 eclosc e20 vxtal gnd 5v xtalpwr vxtal vxtal 1 + c44 10 f c41 0.1 f optional encode circuits vccx vcc l4 ferrite drvddx drvdd l5 ferrite drgnd gnd l2 dnp 05490-060 figure 62. ad9446 evaluation board schematic (continued)
ad9446 rev. 0 | page 32 of 36 c96 0.1 f c97 0.1 f c84 0.1 f c46 0.1 f c22 0.1 f c59 0.1 f c93 0.1 f c94 0.1 f c95 0.1 f 5v gnd c60 0.1 f c10 0.1 f c61 0.1 f c75 0.1 f c27 0.1 f c90 0.1 f c50 0.1 f c30 0.01 f c28 0.1 f c35 0.1 f c32 0.1 f vcc bypass capacitors gnd c31 xx c38 xx c29 xx c19 xx c17 xx c16 xx c15 xx c11 xx c14 xx vcc gnd c37 0.1 f c48 0.1 f c18 0.1 f c53 0.1 f c52 0.1 f c58 0.01 f c56 10 f + c85 0.1 f 5v gnd c110 xx c108 xx c109 xx c72 xx c73 xx 5v gnd c21 0.1 f c20 0.1 f c65 10 f + c47 0.1 f c23 0.1 f drvdd drgnd c64 10 f + c43 0.1 f c45 xx c49 xx c69 xx c70 xx drvdd drgnd c55 10 f + extref gnd 05490-061 figure 63. ad9446 evaluation board schematic (continued)
ad9446 rev. 0 | page 33 of 36 05490-062 rso16iso 220 r8 r7 r6 r5 r4 r3 r1 r2 rso16iso 220 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 rz4 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 rz5 d1o d0o d2o d4o d5o d6o d7o d3o d8o d9o d10o d11o d12o d13o d14o d15o gnd5 vcc6 vcc5 gnd4 end d4y d3y d2y d1y enc c4y c3y c2y c1y gnd3 vcc4 vcc3 gnd2 b4y b3y b2y b1y enb a4y a3y a2y a1y ena gnd1 vcc2 vcc1 gnd d4b d4a d3b d3a d2b d2a d1b d1a c4b c4a c3b c3a c2b c2a c1b c1a b4b b4a b3b b3a b2b b2a b1b b1a a4b a4a a3b a3a a2b a2a a1b a1a 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 u8 sn75lvds386 d15_c/d14_y d14_c/d12_y d13_c/d10_y d12_c/d8_y d11_c/d6_y d10_c/d4_y d9_c/d2_y d3_c d15_t/d14_y d14_t/d13_y d13_t/d11_y d12_t/d9_y d11_t/d7_y d10_t/d5_y d9_t/d3_y d8_t/d1_y d8_c/d0_y d7_t d7_c d6_t d6_c d5_c d5_t d4_t d4_c d3_t d2_t d2_c d1_t d1_c d0_t d0_c drvdd drvdd drgnd drgnd drgnd drvdd drvdd drgnd drvdd drvdd drgnd drvdd drvdd drvdd drvdd drgnd p1 p3 p5 p7 p9 p11 p13 p15 p17 p19 p21 p23 p25 p27 p29 p31 p33 p35 p37 p39 p2 p4 p6 p8 p10 p12 p14 p16 p18 p20 p22 p24 p26 p28 p30 p32 p34 p36 p38 p40 p6 c40ms 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 d14_c/d12_y d12_c/d8_y d10_c/d4_y d8_c/do_y drb d7_c d4_c d3_c d2_c d5_c d6_c d9_c/d2_y d11_c/d6_y d13_c/d10_y d1_c dor_c drgnd d15_c/d14_y drgnd d0_c d14_t/d13_y d12_t/d9_y d10_t/d5_y d8_t/d1_y dr d7_t d4_t d3_t d2_t d5_t d6_t d9_t/d3_y d11_t/d7_y d13_t/d11_y d1_t dor_t/dor_y drgnd d15_t/d15_y drgnd d0_t r8 r7 r6 r5 r4 r3 r1 r2 en_3_4 4y 3y gnd vcc 2y 1y en_1_2 4b 4a 3b 3a 2b 2a 1b 1a 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 u15 sn75lvdt390 r19 0 r20 0 drb dor_c dr dro_t/dor_y dro drvdd drvdd drgnd oro drvdd c76 0.1 f c82 0.1 f c77 0.1 f c78 0.1 f gnd gnd p1 p3 p5 p7 p9 p11 p13 p15 p17 p19 p21 p23 p25 p27 p29 p31 p33 p35 p37 p39 p2 p4 p6 p8 p10 p12 p14 p16 p18 p20 p22 p24 p26 p28 p30 p32 p34 p36 p38 p40 p7 c40ms 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 d15o d13o d11o d9o d8o d7o d4o d3o d2o d5o d6o d10o d12o d14o d1o dro drgnd drgnd gnd?? drgnd oro drgnd d0o figure 64. ad9446 evaluation board schematic (continued)
ad9446 rev. 0 | page 34 of 36 table 11. ad9446 customer evaluation board bill of material item qty. reference designator description package value manufacturer mfg. part no. 1 7 c4, c6, c33, c34, c87, c88, c89 capacitor tajd 10 f digi-key corporation 478-1699-2 2 44 c2, c3, c5, c7, c8, c9, c10, c11, c12, c15, c20, c21, c22, c23, c26, c27, c28, c32, c35, c38, c40, c42, c43, c46, c47, c48, c50, c52, c53, c59, c60, c76, c77, c78, c82, c84, c85, c86, c90, c91, c94, c95, c96, c97 capacitor 402 0.1 f digi-key corporation pcc2146ct-nd 3 2 c30, c58 capacitor 201 0.01 f digi-key corporation 445-1796-1-nd 4 4 c39, c56, c64, c65 capacitor tajd 10 f digi-key corporation 478-1699-2 5 1 c51 capacitor 805 10 f digi-key corporation 490-1717-1-nd 6 1 cr1 diode sot23m5 digi-key corporation ma3x71600lct- nd 7 1 cr2 diode sot23m5 digi-key corporation ma3x71600lct- nd 8 20 e1, e2, e3, e4, e5, e6, e9, e10, e14, e18, e19, e20, e24, e25, e26, e27, e30, e31, e36, e41 header ehole mouser electronics 517-6111tg 9 2 j1, j4 sma sma digi-key corporation arfx1231-nd 10 1 l1 inductor 0603a 10 nh coilcraft, inc. 0603cs-10nxgbu 11 3 l3, l4, l5 emifil? blm31pg500sn1l 1206mil mouser electronics 81-blm31p500s 12 1 p4 pj-002a pj-002a digi-key corporation cp-002a-nd 13 1 p7 header c40ms samtec, inc. tsw-120-08-l-d- ra 14 1 r3 resistor 402 3.74 k digi-key corporation p3.74klct-nd 15 1 r8 resistor 402 50 digi-key corporation p49.9lct-nd 16 4 r10, r19, r39, l2 resistor 402 0 digi-key corporation p0.0jct-nd 17 1 r11 bres402 402 1 k digi-key corporation p1.0klct-nd 18 2 r28, r35 resistor 402 33 digi-key corporation p33jct-nd 19 2 rz4, rz5 resistor array 16pin 22 digi-key corporation 742c163220jct- nd 20 2 t3, t5 transformer adt1-1wt mini-circuits adt1-1wt 21 1 u1 ad9445bsvz-125 sv-100-3 analog devices, inc. ad9445bsvz-100 22 1 u14 adp3338-5 sot- 223hs analog devices, inc. adp3338-5 23 2 u3, u7 adp3338-3.3 sot- 223hs analog devices, inc. adp3338-33 24 1 u8 sn75lvdt386 tssop64 arrow electronics, inc. sn75lvdt386 25 1 u15 sn75lvdt390 soic16pw arrow electronics, inc. sn75lvdt390 26 2 r4, r6 resistor 402 36 digi-key corporation p36jct-nd 27 2 c1, c44, c55 1 capacitor tajd 10 f digi-key corporation 478-1699-2 28 23 c13, c14, c16, c17, c18, c19, c29, c31, c36, c37, c41, c45, c49, c61, c69, c70, c72, c73, c75, c93, c108, c109, c110 1 cap402 402 xx 29 1 c98 1 capacitor 805 10 f digi-key corporation 490-1717-1-nd
ad9446 rev. 0 | page 35 of 36 item qty. reference designator description package value manufacturer mfg. part no. 30 e15 1 header ehole mouser electronics 517-6111tg 31 j5 1 sma sma digi-key corporation arfx1231-nd 32 p6 1 header c40ms samtec, inc. tsw-120-08-l-d- ra 33 2 r1, r2 1 bres402 402 xx 34 3 r5, r7, r9 1 bres402 402 xx 35 1 u2 1 eclosc dip4(14) 36 4 h1, h2, h3, h4 1 mthole6 mthole6 37 2 t1, t2 1 balun transformer sm-22 m/a-com etc1-1-13 38 2 p21, p22 1 term strip ptmicro4 newark electronics 1 parts not populated.
ad9446 rev. 0 | page 36 of 36 outline dimensions compliant to jedec standards ms-026-aed-hd 0.27 0.22 0.17 1 25 26 49 76 100 75 50 14.00 bsc sq 16.00 bsc sq 0.50 bsc lead pitch 0.75 0.60 0.45 1.20 max 1 25 26 50 76 100 75 51 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) bottom view (pins up) 9.50 sq exposed pad notes 1. center figures are typical unless otherwise noted. 2. the package has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to chip ground. it is recommended that no pcb signal traces or vias be located under the package that could come in contact with the conductive slug. attaching the slug to a ground plane will reduce the junction temperature of the device which may be beneficial in high temperature environments. figure 65. 100-lead thin quad fl at package, exposed pad [tqfp_ep] (sv-100-3) dimensions shown in millimeters ordering guide model temperature range package description package option ad9446bsvz-80 1 C40c to +85c 100-lead tqfp_ep sv-100-3 ad9446bsvz-100 1 C40c to +85c 100-lead tqfp_ep sv-100-3 AD9446-100LVDS/pcb ad9446-100 lvds mode evaluation board ad9446-80lvds/pcb ad9446-80 lvds mode evaluation board 1 z = pb-free part. ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05490C0C10/05(0)

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